1. Technical Field
This invention relates generally to electronic devices, and more particularly, to an approach for testing Metal-Insulator-Metal (MIM) devices for development thereof.
2. Background Art
FIG. 1 illustrates a two-terminal metal-insulator-metal (MIM) resistive memory device 30. The memory device 30 includes a metal, for example copper electrode 32, an active layer 34 of for example copper oxide on and in contact with the electrode 32, and a metal, for example copper electrode 36 on and in contact with the active layer 34. As an example of the operation of such a device 30, with reference to FIG. 2, initially, assuming that the memory device 30 is unprogrammed, in order to program the memory device 30, ground is applied to the electrode 32, while a positive voltage is applied to electrode 36, so that an electrical potential Vpg (the “programming” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. Upon removal of such potential the memory device 30 remains in a conductive or low-resistance state having an ON-state resistance.
In the read step of the memory device 30 in its programmed (conductive) state, an electrical potential Vr (the “read” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32. This electrical potential is less than the electrical potential Vpg applied across the memory device 30 for programming (see above). In this situation, the memory device 30 will readily conduct current, which indicates that the memory device 30 is in its programmed state.
In order to erase the memory device 30, a positive voltage is applied to the electrode 32, while the electrode 36 is held at ground, so that an electrical potential Ver (the “erase” electrical potential) is applied across the memory device 30 from a higher to a lower electrical potential in the direction of from electrode 32 to electrode 36.
In the read step of the memory device 30 in its erased (substantially non-conductive) state, the electrical potential Vr is again applied across the memory device 30 from a higher to a lower electrical potential in the direction from electrode 36 to electrode 32 as described above. With the active layer 34 (and memory device 30) in a high-resistance or substantially non-conductive OFF state, the memory device 30 will not conduct significant current, which indicates that the memory device 30 is in its erased state.
It will be understood that the development of MIM devices is ongoing, as is clearly desirable to improve the performance thereof (for example, improved switching speed and data retention, improved immunity to performance degradation at elevated temperatures, etc.)
Therefore, what is needed is an approach for testing MIM devices which promotes development of these devices, by being simple in design and fabrication and effective in use.